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19-4226; Rev 1; 10/08
Dual-Channel, 10-Bit, 100Msps ADC
General Description
The MAX19516 dual-channel, analog-to-digital converter (ADC) provides 10-bit resolution and a maximum sample rate of 100Msps. The MAX19516 analog input accepts a wide 0.4V to 1.4V input common-mode voltage range, allowing DCcoupled inputs for a wide range of RF, IF, and baseband front-end components. The MAX19516 provides excellent dynamic performance from baseband to high input frequencies beyond 400MHz, making the device ideal for zero-intermediate frequency (ZIF) and highintermediate frequency (IF) sampling applications. The typical signal-to-noise ratio (SNR) performance is 60dBFS and typical spurious-free dynamic range (SFDR) is 82dBc at fIN = 70MHz and fCLK = 100MHz. The MAX19516 operates from a 1.8V supply. Additionally, an integrated, self-sensing voltage regulator allows operation from a 2.5V to 3.3V supply (AVDD). The digital output drivers operate on an independent supply voltage (OVDD) over the 1.8V to 3.5V range. The analog power consumption is only 57mW per channel at V AVDD = 1.8V. In addition to low operating power, the MAX19516 consumes only 1mW in powerdown mode and 17mW in standby mode. Various adjustments and feature selections are available through programmable registers that are accessed through the 3-wire serial-port interface. Alternatively, the serial-port interface can be disabled, with the three pins available to select output mode, data format, and clock-divider mode. Data outputs are available through a dual parallel CMOS-compatible output data bus that can also be configured as a single multiplexed parallel CMOS bus. The MAX19516 is available in a small 7mm x 7mm 48pin thin QFN package and is specified over the -40C to +85C extended temperature range. Refer to the MAX19505, MAX19506, and MAX19507 data sheets for pin- and feature-compatible 8-bit, 65Msps, 100Msps, and 130Msps versions, respectively. Refer to the MAX19515 and MAX19517 data sheets for pin- and feature-compatible 10-bit, 65Msps and 130Msps versions, respectively.
Features
o Very-Low-Power Operation (57mW/Channel at 100Msps) o 1.8V or 2.5V to 3.3V Analog Supply o Excellent Dynamic Performance 60dBFS SNR at 70MHz 82dBc SFDR at 70MHz o User-Programmable Adjustments and Feature Selection through an SPITM Interface o Selectable Data Bus (Dual CMOS or Single Multiplexed CMOS) o DCLK Output and Programmable Data Output Timing Simplifies High-Speed Digital Interface o Very Wide Input Common-Mode Voltage Range (0.4V to 1.4V) o Very High Analog Input Bandwidth (> 850MHz) o Single-Ended or Differential Analog Inputs o Single-Ended or Differential Clock Input o Divide-by-One (DIV1), Divide-by-Two (DIV2), and Divide-by-Four (DIV4) Clock Modes o Two's Complement, Gray Code, and Offset Binary Output Data Format o Out-of-Range Indicator (DOR) o CMOS Output Internal Termination Options (Programmable) o Reversible Bit Order (Programmable) o Data Output Test Patterns o Small 7mm x 7mm 48-Pin Thin QFN Package with Exposed Pad
MAX19516
Ordering Information
PART MAX19516ETM+ TEMP RANGE -40C to +85C PIN-PACKAGE 48 TQFN-EP*
Applications
IF and Baseband Communications, Including Cellular Base Stations and Point-to-Point Microwave Receivers Ultrasound and Medical Imaging Portable Instrumentation and Low-Power Data Acquisition Digital Set-Top Boxes
+Denotes a lead-free/RoHS-compliant package. *EP = Exposed pad.
Pin Configuration appears at end of data sheet. SPI is a trademark of Motorola, Inc.
1
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual-Channel, 10-Bit, 100Msps ADC MAX19516
ABSOLUTE MAXIMUM RATINGS
OVDD, AVDD to GND............................................-0.3V to +3.6V CMA, CMB, REFIO, INA+, INA-, INB+, INB- to GND ......................................................-0.3V to +2.1V CLK+, CLK-, SYNC, SPEN, CS, SCLK, SDIN to GND ..........-0.3V to the lower of (VAVDD + 0.3V) and +3.6V DCLKA, DCLKB, D9A-D0A, D9B-D0B, DORA, DORB to GND..........-0.3V to the lower of (VOVDD + 0.3V) and +3.6V Continuous Power Dissipation (TA = +70C) 48-Pin Thin QFN, 7mm x 7mm x 0.8mm (derate 40mW/C above +70C).............................................................3200mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 100MHz, AIN = -0.5dBFS, data output termination = 50, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Differential Input-Voltage Range Common-Mode Input-Voltage Range Input Resistance INL DNL OE GE VDIFF VCM fIN = 3MHz fIN = 3MHz Internal reference External reference = 1.25V Differential or single-ended inputs (Note 2) Fixed resistance RIN Differential input resistance, common mode connected to inputs Switched capacitance input current, each input Fixed capacitance to ground, each input Switched capacitance, each input 100 50 Figures 9, 10 9 0.4 > 100 4 54 0.7 1.2 k -0.8 -0.7 -0.4 -1.5 10 0.25 0.2 0.1 0.3 1.5 1.4 +0.8 +0.7 +0.4 +1.5 Bits LSB LSB %FS %FS VP-P V SYMBOL CONDITIONS MIN TYP MAX UNITS
ANALOG INPUTS (INA+, INA-, INB+, INB-) (Figure 3)
Input Current Input Capacitance CONVERSION RATE Maximum Clock Frequency Minimum Clock Frequency Data Latency
IIN CPAR CSAMPLE fCLK fCLK
A pF
MHz MHz Cycles
2
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Dual-Channel, 10-Bit, 100Msps ADC
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 100MHz, AIN = -0.5dBFS, data output termination = 50, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER DYNAMIC PERFORMANCE Small-Signal Noise Floor Signal-to-Noise Ratio SSNF SNR fIN = 70MHz, < -35dBFS fIN = 3MHz fIN = 70MHz fIN = 175MHz Signal-to-Noise Plus Distortion Ratio fIN = 3MHz SINAD fIN = 70MHz fIN = 175MHz Spurious-Free Dynamic Range (2nd and 3rd Harmonic) fIN = 3MHz SFDR1 fIN = 70MHz fIN = 175MHz Spurious-Free Dynamic Range (4th and Higher Harmonics) fIN = 3MHz SFDR2 fIN = 70MHz fIN = 175MHz fIN = 3MHz Second Harmonic HD2 fIN = 70MHz fIN = 175MHz fIN = 3MHz Third Harmonic HD3 fIN = 70MHz fIN = 175MHz fIN = 3MHz Total Harmonic Distortion THD fIN = 70MHz fIN = 175MHz Third-Order Intermodulation Full-Power Bandwidth Aperture Delay Aperture Jitter Overdrive Recovery Time IM3 FPBW tAD tAJ 10% beyond full scale fIN = 70MHz 1.5MHz, -7dBFS fIN = 175MHz 2.5MHz, -7dBFS 74 72.2 58.3 58.9 -60.3 60.1 60.0 59.7 59.6 59.5 59.2 84 83 80 82 82 82 -84 -83 -80 -86 -86 -82 -80 -79 -77 -90 -80 850 850 0.3 1 dBc MHz ps psRMS Cycles -70.5 dBc -74 dBc -72.2 dBc dBc dBc dB dBFS dBFS SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX19516
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3
Dual-Channel, 10-Bit, 100Msps ADC MAX19516
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 100MHz, AIN = -0.5dBFS, data output termination = 50, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS fINA or fINB = 70MHz at -1dBFS fINA or fINB = 175MHz at -1dBFS fIN = 70MHz fIN = 70MHz fIN = 70MHz VCOM VREFOUT TCREF Default programmable setting 0.85 1.23 MIN TYP 95 85 0.05 0.1 0.5 0.9 1.25 < 60 1.25 +5/ -10% 10 20% 0.4 to 2.0 Self-biased DC-coupled clock signal Differential, default Input Resistance Input Capacitance Single-Ended Mode Selection Threshold (VCLK-) Allowable Logic Swing (VCLK+) Single-Ended Clock Input High Threshold (VCLK+) Single-Ended Clock Input Low Threshold (VCLK+) Input Leakage (CLK+) Input Leakage (CLK-) Input Capacitance (CLK+) VCLK+ = VAVDD = 1.8V or 3.3V VCLK+ = 0 VCLK- = 0 -0.5 -150 3 -50 1.5 0.3 +0.5 0 - VAVDD RCLK CCLK Differential, internal termination selected Common mode To ground, each input CLOCK INPUTS (CLK+, CLK-)--SINGLE-ENDED MODE (VCLK- < 0.1V) 0.1 V V V V A A pF 1.2 1.0 to 1.4 10 100 9 3 0.95 1.27 MAX UNITS
INTERCHANNEL CHARACTERISTICS Crosstalk Gain Match Offset Match Phase Match ANALOG OUTPUTS (CMA, CMB) CMA, CMB Output Voltage INTERNAL REFERENCE REFIO Output Voltage REFIO Temperature Coefficient EXTERNAL REFERENCE REFIO Input-Voltage Range REFIO Input Resistance VREFIN RREFIN V k V ppm/C V dBc dB %FSR Degrees
CLOCK INPUTS (CLK+, CLK-)--DIFFERENTIAL MODE Differential Clock Input Voltage Differential Input Common-Mode Voltage VP-P V k k pF
4
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Dual-Channel, 10-Bit, 100Msps ADC
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 100MHz, AIN = -0.5dBFS, data output termination = 50, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER CLOCK INPUTS (SYNC) Allowable Logic Swing Sync Clock Input High Threshold Sync Clock Input Low Threshold Input Leakage Input Capacitance DIGITAL INPUTS (SHDN, SPEN) Allowable Logic Swing Input High Threshold Input Low Threshold Input Leakage Input Capacitance Allowable Logic Swing Input High Threshold Input Low Threshold Input Leakage Input Capacitance CDIN VSCLK/VSDIN/VCS = VAVDD = 1.8V VSCLK/VSDIN/VCS = VAVDD = 3.3V VSCLK/VSDIN/VCS = 0, VAVDD = 1.8V VSCLK/VSDIN/VCS = 0, VAVDD = 3.3V VOC I = 0V, VAVDD = 1.8V I = 0V, VAVDD = 3.3V ISINK = 200A ISOURCE = 200A VOVDD applied GND applied -0.5 VOVDD - 0.2 +0.5 7 16 -65 -105 1.35 2.58 VSCLK/VSDIN/VCS = VAVDD = 1.8V or 3.3V VSCLK/VSDIN/VCS = 0 -0.5 3 12 21 -50 -90 1.45 2.68 17 26 -35 -75 1.55 2.78 0.2 1.5 0.3 +0.5 CDIN VSHDN/VSPEN = VAVDD = 1.8V or 3.3V VSHDN/VSPEN = 0 -0.5 3 0 - VAVDD 1.5 0.3 +0.5 0 - VAVDD V V V A pF V V V A pF VSYNC = VAVDD = 1.8V or 3.3V VSYNC = 0 -0.5 4.5 1.5 0.3 +0.5 0 - VAVDD V V V A pF SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX19516
SERIAL-PORT INPUTS (SCLK, SDIN, CS, where SPEN = 0V)--SERIAL-PORT CONTROL MODE
SERIAL-PORT INPUTS (SCLK, SDIN, CS, where SPEN = VAVDD)--PARALLEL CONTROL MODE (Figure 5) Input Pullup Current Input Pulldown Current Open-Circuit Voltage A A V
DIGITAL OUTPUTS (75, D0-D9 (A and B Channel), DCLKA, DCLKB, DORA, DORB) Output-Voltage Low Output-Voltage High Three-State Leakage Current VOL VOH ILEAK V V A
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5
Dual-Channel, 10-Bit, 100Msps ADC MAX19516
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 100MHz, AIN = -0.5dBFS, data output termination = 50, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Wake-Up Time from Shutdown Wake-Up Time from Standby SCLK Period SCLK to CS Setup Time SCLK to CS Hold Time SDIN to SCLK Setup Time SDIN to SCLK Hold Time SCLK to SDIN Output Data Delay Clock Pulse-Width High Clock Pulse-Width Low Clock Duty Cycle Data Delay After Rising Edge of CLK+ Data to DCLK Setup Time Data to DCLK Hold Time Clock Pulse-Width High Clock Pulse-Width Low Clock Duty Cycle Data Delay After Rising Edge of CLK+ Data to DCLK Setup Time Data to DCLK Hold Time DCLK Duty Cycle MUX Data Duty Cycle Setup Time for Valid Clock Edge Hold-Off Time for Invalid Clock Edge Minimum Synchronization Pulse Width SYMBOL tWAKE tWAKE tSCLK tCSS tCSH tSDS tSDH tSDD tCH tCL tCH/tCLK tDD tSETUP tHOLD tCH tCL tCH/tCLK tDD tSETUP tHOLD tDCH/tCLK tCHA/tCLK tSUV tHO CL = 10pF, VOVDD = 1.8V (Note 2) CL = 10pF, VOVDD = 3.3V CL = 10pF, VOVDD = 1.8V (Note 2) CL = 10pF, VOVDD = 1.8V (Note 2) CL = 10pF, VOVDD = 1.8V (Note 2) CL = 10pF, VOVDD = 1.8V (Note 2) Edge mode (Note 2) Edge mode (Note 2) Relative to input clock period 2.8 -0.2 42 40 0.7 0.5 2 2.6 CL = 10pF, VOVDD = 1.8V (Note 2) CL = 10pF, VOVDD = 3.3V CL = 10pF, VOVDD = 1.8V (Note 2) CL = 10pF, VOVDD = 1.8V (Note 2) 8.2 0.7 2.9 Serial-data write Serial-data write Serial-data read 5.0 5.0 30 to 70 4.8 3.6 8.8 1.2 5.0 5.0 30 to 70 4.4 3.5 4.0 1.0 50 50 59 65 6.5 6.6 CONDITIONS Internal reference, CREFIO = 0.1F (10) Internal reference 50 10 10 10 0 10 MIN TYP 5 15 MAX UNITS ms s ns ns ns ns ns ns ns ns % ns ns ns ns ns % ns ns ns % % ns ns Cycles
POWER-MANAGEMENT CHARACTERISTICS
SERIAL-PORT INTERFACE TIMING (Note 2) (Figure 7)
TIMING CHARACTERISTICS--DUAL BUS PARALLEL MODE (Figure 9) (Default Timing, see Table 5)
TIMING CHARACTERISTICS--MULTIPLEXED BUS PARALLEL MODE (Figure 10) (Default Timing, see Table 5)
TIMING CHARACTERISTICS--SYNCHRONIZATION (Figure 12)
6
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Dual-Channel, 10-Bit, 100Msps ADC
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 100MHz, AIN = -0.5dBFS, data output termination = 50, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER POWER REQUIREMENTS Low-level VAVDD Analog Supply Voltage Digital Output Supply Voltage VAVDD VOVDD Dual channel Single channel active Analog Supply Current IAVDD Standby mode Power-down mode Power-down mode, VAVDD = 3.3V Dual channel Dual channel, VAVDD = 3.3V Analog Power Dissipation PDA Single channel active Standby mode Power-down mode Power-down mode, VAVDD = 3.3V Digital Output Supply Current IOVDD Dual-channel mode, CL = 10pF Power-down mode High-level VAVDD (regulator mode, invoked automatically) 1.7 2.3 1.7 63 37 9.5 0.65 1.6 113 208 67 17 1.2 2.9 20 < 0.1 mA 24 1.6 mW 139 13 0.9 mA 1.9 3.5 3.5 77 V V SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX19516
Note 1: Specifications +25C guaranteed by production test, specifications < +25C guaranteed by design and characterization. Note 2: Guaranteed by design and characterization.
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Dual-Channel, 10-Bit, 100Msps ADC MAX19516
Typical Operating Characteristics
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 100MHz, AIN = -0.5dBFS, data output termination = 50, TA = +25C, unless otherwise noted.)
3MHz INPUT FFT PLOT
MAX19516 toc01
3MHz SINGLE-ENDED INPUT FFT PLOT
MAX19516 toc02
70MHz INPUT FFT PLOT
fIN = 70.0935363MHz AIN = -0.473dBFS SNR = 59.422dB SINAD = 59.398dB THD = -81.978dBc SFDR1 = 88.062dBc SFDR2 = 86.514dBc
MAX19516 toc03
0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 0 5 fIN = 2.99911499MHz AIN = -0.446dBFS SNR = 59.591dB SINAD = 59.566dB THD = -82.007dBc SFDR1 = 90.747dBc SFDR2 = 86.163dBc
0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 fIN = 2.99911499MHz AIN = -0.474dBFS SNR = 59.139dB SINAD = 58.968dB THD = -73.092dBc SFDR1 = 74.814dBc SFDR2 = 79.872dBc
0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120
10 15 20 25 30 35 40 45 50 FREQUENCY (MHz)
0
5
10 15 20 25 30 35 40 45 50 FREQUENCY (MHz)
0
5
10 15 20 25 30 35 40 45 50 FREQUENCY (MHz)
175MHz INPUT FFT PLOT
MAX19516 toc04
70MHz TWO-TONE IMD PLOT
MAX19516 toc05
175MHz TWO-TONE IMD PLOT
fIN1 = 177.29835MHz fIN2 = 172.40028MHz
MAX19516 toc06
0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120 0 fIN = 175.489044MHz AIN = -0.506dBFS SNR = 59.222dB SINAD = 59.187dB THD = -80.109dBc SFDR1 = 87.850dBc SFDR2 = 83.290dBc
0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120
fIN1 = 68.4169769MHz fIN2 = 71.4000701MHz
0 -20 AMPLITUDE (dBFS) -40 -60 -80 -100 -120
5 10 15 20 25 30 35 40 45 50 FREQUENCY (MHz)
0
5
10 15 20 25 30 35 40 45 50 FREQUENCY (MHz)
0
5
10 15 20 25 30 35 40 45 50 FREQUENCY (MHz)
INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE
MAX19516 toc07
DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE
MAX19516 toc08
PERFORMANCE vs. INPUT FREQUENCY
SFDR2 90 85 PERFORMANCE (dBFS) 80 75 70 65 60 55 SNR 50 SINAD -THD SFDR1
MAX19516 toc09
1.0 0.8 0.6 0.4
1.0 0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
95
INL (LSB)
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 256 512 768 DIGITAL OUTPUT CODE 1024
0
256 512 768 DIGITAL OUTPUT CODE
1024
0
50
100 150 200 250 300 350 400 INPUT FREQUENCY (MHz)
8
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Dual-Channel, 10-Bit, 100Msps ADC
Typical Operating Characteristics (continued)
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 100MHz, AIN = -0.5dBFS, data output termination = 50, TA = +25C, unless otherwise noted.)
SINGLE-ENDED PERFORMANCE vs. INPUT FREQUENCY
MAX19516 toc10
MAX19516
PERFORMANCE vs. ANALOG INPUT AMPLITUDE
MAX19516 toc11
PERFORMANCE vs. SAMPLING FREQUENCY
95 90 PERFORMANCE (dBFS) 85 80 75 70 65 60 55 SINAD 60 65 70 75 80 85 90 95 100 105 110 SAMPLING FREQUENCY (Msps) SNR -THD SFDR2 SFDR1
MAX19516 toc12
85 SFDR2 SINGLE-ENDED PERFORMANCE (dBFS) 80 75 70 65 60 55 50 0 10 20 30 40 50 INPUT FREQUENCY (MHz) 60 SINAD SNR -THD SFDR1
110 100 PERFORMANCE (dBFS) 90 80 70 60 50 SNR -THD SFDR1 SFDR2
100
SINAD
50 -60 -50 -40 -30 -20 -10 ANALOG INPUT AMPLITUDE (dBFS) 0
70
PERFORMANCE vs. COMMON-MODE VOLTAGE
MAX19516 toc13
PERFORMANCE vs. ANALOG SUPPLY VOLTAGE
MAX19516 toc14
PERFORMANCE vs. ANALOG SUPPLY VOLTAGE
SFDR1 90 85 PERFORMANCE (dBFS) 80 75 70 65 60 SNR SFDR2 -THD
MAX19516 toc15
110 SFDR1 100 PERFORMANCE (dBFS) 90 80 70 60 SNR -THD SFDR2
95 SFDR1 90 85 PERFORMANCE (dBFS) SFDR2 80 75 70 65 60 55 SNR -THD
95
SINAD 50 0.35 0.55 0.75 0.95 1.15 1.35 COMMON-MODE VOLTAGE (V)
SINAD 1.65 1.70 1.75 1.80 1.85 1.90 ANALOG SUPPLY VOLTAGE (V) 1.95
55 50 2.3
SINAD 2.5 2.7 2.9 3.1 3.3 ANALOG SUPPLY VOLTAGE (V) 3.5
50
ANALOG SUPPLY CURRENT vs. SAMPLING FREQUENCY
MAX19516 toc16
ANALOG SUPPLY CURRENT vs. TEMPERATURE
MAX19516 toc17
ANALOG SUPPLY CURRENT vs. SUPPLY VOLTAGE
69
MAX19516 toc18
68 66 ANALOG SUPPLY CURRENT (mA) 64 62 60 58 56 54 52 50
69 ANALOG SUPPLY CURRENT (mA) 67 65 63 61 59 57 55
ANALOG SUPPLY CURRENT (mA)
67 65 63 61 59 57 55
60 65 70 75 80 85 90 95 100 105 110 SAMPLING FREQUENCY (MHz)
-40
-20
0 20 40 TEMPERATURE (C)
60
80
1.65
1.70
1.75 1.80 1.85 SUPPLY VOLTAGE (V)
1.90
1.95
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Dual-Channel, 10-Bit, 100Msps ADC MAX19516
Typical Operating Characteristics (continued)
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 100MHz, AIN = -0.5dBFS, data output termination = 50, TA = +25C, unless otherwise noted.)
ANALOG SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX19516 toc19
DIGITAL SUPPLY CURRENT vs. SAMPLING FREQUENCY
MAX19516 toc20
DIGITAL SUPPLY CURRENT vs. SAMPLING FREQUENCY
OVDD = 3.6V 35 DIGITAL SUPPLY CURRENT (mA) 30 25 20 15 10 5 0
MAX19516 toc21
67.5 ANALOG SUPPLY CURRENT (mA) 67.0 66.5 66.0 65.5 65.0 64.5 64.0 2.3 2.5 2.7 2.9 3.1 SUPPLY VOLTAGE (V) 3.3
20 18 DIGITAL SUPPLY CURRENT (mA) 16 14 12 10 8 6
4
40
OVDD = 1.8V
2 0 3.5 60 65 70 75 80 85 90 95 100 105 110 SAMPLING FREQUENCY (Msps)
60 65 70 75 80 85 90 95 100 105 110 SAMPLING FREQUENCY (Msps)
DIGITAL SUPPLY CURRENT vs. TEMPERATURE
MAX19516 toc22
DIGITAL SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX19516 toc23
DIGITAL SUPPLY CURRENT vs. SUPPLY VOLTAGE
45 DIGITAL SUPPLY CURRENT (mA) 40 35 30 25 20 15 10 5 MULTIPLEXED BUS
MAX19516 toc24
35 33 DIGITAL SUPPLY CURRENT (mA) 31 29 27 25 23 21 19 17 15 -40 -20 0 20 40 TEMPERATURE (C) 60 80 OVDD = 1.8V OVDD = 3.6V
30 DUAL BUS DIGITAL SUPPLY CURRENT (mA) 25 20 15 10 5 0 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 SUPPLY VOLTAGE (V)
50
0 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 SUPPLY VOLTAGE (V)
PERFORMANCE vs. CLOCK DUTY CYCLE
MAX19516 toc25
PERFORMANCE vs. TEMPERATURE
90 85 PERFORMANCE (dBFS) 80 75 70 65 60 55 SINAD SNR SFDR2 -THD SFDR1
MAX19516 toc26
GAIN ERROR vs. TEMPERATURE
0.04 0.03 GAIN ERROR (%) 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 -0.05
MAX19516 toc27
95 SFDR1 90 PERFORMANCE (dBFS) 85 80 75 70 65 60 SINAD 55 30 35 40 45 50 55 CLOCK DUTY CYCLE (%) 60 SNR -THD SFDR2
95
0.05
50 65 -40 -20 0 20 40 TEMPERATURE (C) 60 80
-40
-20
0 20 40 TEMPERATURE (C)
60
80
10
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Dual-Channel, 10-Bit, 100Msps ADC
Typical Operating Characteristics (continued)
(VAVDD = VOVDD = 1.8V, internal reference, differential clock, VCLK = 1.5VP-P, fCLK = 100MHz, AIN = -0.5dBFS, data output termination = 50, TA = +25C, unless otherwise noted.)
COMMON-MODE REFERENCE VOLTAGE vs. TEMPERATURE
COMMON-MODE REFERENCE VOLTAGE (V) VCM = 1.35V 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 -40 -20 0 20 40 TEMPERATURE (C) 60 80 -40 -20 0 20 40 TEMPERATURE (C) 60 80 VCM = 0.45V VCM = 1.2V VCM = 1.05V VCM = 0.9V VCM = 0.75V VCM = 0.6V
MAX19516 toc30
MAX19516
OFFSET ERROR vs. TEMPERATURE
MAX19516 toc28
REFERENCE VOLTAGE vs. TEMPERATURE
MAX19516 toc29
0.2 0.1 0 OFFSET ERROR (mV) -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -40 -20 0 20 40 TEMPERATURE (C) 60 80
1.2516
1.6
REFERENCE VOLTAGE (V)
1.2495
1.2474
1.2453
1.2432
GAIN ERROR vs. SUPPLY VOLTAGE
0.06 0.04 GAIN ERROR (%) 0.02 0 -0.02 -0.04 -0.06 -0.08 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 SUPPLY VOLTAGE (V) 40 30 REGULATOR MODE
MAX19516 toc31
INPUT CURRENT vs. COMMON-MODE VOLTAGE
MAX19516 toc32
0.08
90 80 INPUT CURRENT (A) 70 60 50
0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 COMMON-MODE VOLTAGE (V)
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11
Dual-Channel, 10-Bit, 100Msps ADC MAX19516
Pin Description
PIN 1, 12, 13, 48 2 3 4 5 6 7 8 9 10 11 14 15 16 17, 18 19 20 21 22 23 24 25, 36 26 27 28 29 30 31 32 33 34 35 37 38 39 NAME AVDD CMA INA+ INASPEN REFIO SHDN I.C. INB+ INBCMB SYNC CLK+ CLKGND DORB DCLKB D0B D1B D2B D3B OVDD D4B D5B D6B D7B D8B D9B D0A D1A D2A D3A D4A D5A D6A FUNCTION Analog Supply Voltage. Bypass each AVDD input pair (1, 48) and (12, 13) to GND with 0.1F. Channel A Common-Mode Input-Voltage Reference Channel A Positive Analog Input Channel A Negative Analog Input Active-Low SPI Enable. Drive high to enable parallel programming mode. Reference Input/Output. To use internal reference, bypass to GND with a > 0.1F capacitor. See the Reference Input/Output (REFIO) section for external reference adjustment. Active-High Power-Down. If SPEN is high (parallel programming mode), a register reset is initiated on the falling edge of SHDN. Internally Connected. Leave unconnected. Channel B Positive Analog Input Channel B Negative Analog Input Channel B Common-Mode Input-Voltage Reference Clock-Divider Mode Synchronization Input Clock Positive Input Clock Negative Input. If CLK- is connected to ground, CLK+ is a single-ended logic-level clock input. Otherwise, CLK+/CLK- are self-biased differential clock inputs. Ground. Connect all ground inputs and EP (exposed pad) together. Channel B Data Over Range Channel B Data Clock Channel B Three-State Digital Output, Bit 0 (LSB) Channel B Three-State Digital Output, Bit 1 Channel B Three-State Digital Output, Bit 2 Channel B Three-State Digital Output, Bit 3 Digital Supply Voltage. Bypass each OVDD input to GND with 0.1F capacitor. Channel B Three-State Digital Output, Bit 4 Channel B Three-State Digital Output, Bit 5 Channel B Three-State Digital Output, Bit 6 Channel B Three-State Digital Output, Bit 7 Channel B Three-State Digital Output, Bit 8 Channel B Three-State Digital Output, Bit 9 (MSB) Channel A Three-State Digital Output, Bit 0 (LSB) Channel A Three-State Digital Output, Bit 1 Channel A Three-State Digital Output, Bit 2 Channel A Three-State Digital Output, Bit 3 Channel A Three-State Digital Output, Bit 4 Channel A Three-State Digital Output, Bit 5 Channel A Three-State Digital Output, Bit 6
12
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Dual-Channel, 10-Bit, 100Msps ADC
Pin Description (continued)
PIN 40 41 42 43 44 45 46 47 -- NAME D7A D8A D9A DORA DCLKA SDIN/FORMAT SCLK/DIV CS/OUTSEL EP Channel A Three-State Digital Output, Bit 7 Channel A Three-State Digital Output, Bit 8 Channel A Three-State Digital Output, Bit 9 (MSB) Channel A Data Over Range Channel A Data Clock SPI Data Input/Format. Serial-data input when SPEN is low. Output data format when SPEN is high. Serial Clock/Clock Divider. Serial clock when SPEN is low. Clock divider when SPEN is high. Serial-Port Select/Data Output Mode. Serial-port select when SPEN is low. Data output mode selection when SPEN is high. Exposed Pad. Internally connected to GND. Connect to a large ground plane to maximize thermal performance. FUNCTION
MAX19516
Detailed Description
The MAX19516 uses a 10-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle. From input to output the total latency is 9 clock cycles. Each pipeline converter stage converts its input voltage to a digital output code. At every stage, except the last, the error between the input voltage and the digital output code is multiplied and passed on to the next pipeline stage. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. Figure 2 shows the MAX19516 functional diagram.
+ MAX19516
FLASH ADC DAC
-
x2
IN_+ STAGE 1 IN_DIGITAL ERROR CORRECTION STAGE 2 STAGE 9
STAGE 10 END OF PIPELINE
D0_ THROUGH D9_
Analog Inputs and Common-Mode Reference
Apply the analog input signal to the analog inputs (INA+/INA- or INB+/INB-), which are connected to the input sampling switch (Figure 3). When the input sampling switch is closed, the input signal is applied to the sampling capacitors through the input switch resistance. The input signal is sampled at the instant the input switch opens. The pipeline ADC processes the sampled voltage and the digital output result is available 9 clock cycles later. Before the input switch is closed to begin the next sampling cycle, the sampling capacitors are reset to the input common-mode potential. Common-mode bias can be provided externally or internally through 2k resistors. In DC-coupled applications, the signal source provides the external bias and the bias current. In AC-coupled applications, the input
Figure 1. Pipeline Architecture--Stage Blocks
current is supplied by the common-mode input voltage. For example, the input current can be supplied through the center tap of a transformer secondary winding. Alternatively, program the appropriate internal register through the serial-port interface to supply the input DC current through internal 2k resistors (Figure 3). When the input current is supplied through the internal resistors, the input common-mode potential is reduced by the voltage drop across the resistors. The commonmode input reference voltage can be adjusted through programmable register settings from 0.45V to 1.35V in 0.15V increments. The default setting is 0.90V. Use this feature to provide a common-mode output reference to a DC-coupled driving circuit.
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13
Dual-Channel, 10-Bit, 100Msps ADC MAX19516
CLOCK
MAX19516
INA+ T/H INAPIPELINE ADC DIGITAL ERROR CORRECTION DATA AND OUTPUT FORMAT D0A-D9A DORA DCLKA CMA REFIO CMB REFERENCE AND BIAS SYSTEM INTERNAL REFERENCE GENERATOR OUTPUT DRIVERS OVDD (1.8V TO 3.3V) D0B-D9B INB+ T/H INBPIPELINE ADC DIGITAL ERROR CORRECTION CLOCK CLK+ CLKSYNC CS SCLK SDIN SPEN SERIAL PORT AND CONTROL REGISTERS DUTYCYCLE EQUALIZER REGULATOR AND POWER CONTROL AVDD (1.8V OR 2.5V TO 3.3V) DORB DCLKB
CLOCK DIVIDER
1.8V INTERNAL
SHDN
INTERNAL CONTROL
GND
Figure 2. Functional Diagram
AVDD CMA INA+ 2k CPAR 0.7pF CSAMPLE 1.2pF RSWITCH 120
*VCOM AVDD 2k INACPAR 0.7pF CSAMPLE 1.2pF RSWITCH 120
SAMPLING CLOCK
MAX19516
*VCOM PROGRAMMABLE FROM 0.45V TO 1.35V. SEE COMMON-MODE REGISTER (08h)
Figure 3. Internal Track-and-Hold (T/H) Circuit
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Dual-Channel, 10-Bit, 100Msps ADC MAX19516
29/32 AVDD INTERNAL GAIN--BYPASS REFIO EXTERNAL GAIN CONTROL--DRIVE REFIO 0.1F EXTERNAL BYPASS AVDD 36k REFIO 1.250V BANDGAP REFERENCE BUFFER CS SCLK SDIN 156k 3/32 AVDD 23/32 AVDD
DECODER
TO CONTROL LOGIC
10k
SCALE AND INTERNAL REFERENCE LEVEL SHIFT (CONTROLS ADC GAIN)
Figure 4. Simplified Reference Schematic
Figure 5. Simplified Parallel-Interface Input Schematic
Table 1. Parallel-Interface Pin Functionality
SPEN 0 1 1 1 1 1 1 1 1 1 SDIN/FORMAT SDIN 0 AVDD Unconnected X X X X X X SCLK/DIV SCLK X X X 0 AVDD Unconnected X X X CS/OUTSEL CS X X X X X X 0 AVDD Unconnected DESCRIPTION SPI interface active. Features are programmed through the serial port (see the Serial Programming Interface section). Two's complement Offset binary Gray code Clock divide-by-1 Clock divide-by-2 Clock divide-by-4 CMOS (dual bus) MUX CMOS (channel A data bus) MUX CMOS (channel B data bus)
X = Don't care.
Reference Input/Output (REFIO)
REFIO adjusts the reference potential, which, in turn, adjusts the full-scale range of the ADC. Figure 4 shows a simplified schematic of the reference system. An internal bandgap voltage generator provides an internal reference voltage. The bandgap potential is buffered and applied to REFIO through a 10k resistor. Bypass REFIO with a 0.1F capacitor to AGND. The bandgap voltage is applied to a scaling and level-shift circuit, which creates internal reference potentials that establish the full-scale range of the ADC. Apply an external voltage on REFIO to trim the ADC full scale. The allowable adjustment range is +5/-15%. The REFIO-to-ADC gain transfer function is: VFS = 1.5 x [VREFIO/1.25] Volts
Programming and Interface
There are two ways to control the MAX19516 operating modes. Full feature selection is available using the SPI interface, while the parallel interface offers a limited set of commonly used features. The programming mode is selected using the SPEN input. Drive SPEN low for SPI interface; drive SPEN high for parallel interface.
Parallel Interface
The parallel interface offers a pin-programmable interface with a limited feature set. Connect SPEN to AVDD to enable the parallel interface. See Table 1 for pin functionality; see Figure 5 for a simplified parallel-interface input schematic.
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15
Dual-Channel, 10-Bit, 100Msps ADC MAX19516
CS
SCLK
SDIN
R/W
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
R/W 0 = WRITE 1 = READ
ADDRESS
DATA WRITE OR READ
Figure 6. Serial-Interface Communication Cycle
tCSH
tCSS CS
tSCLK
SCLK
tSDS
tSDH
tSDD
SDIN
WRITE
READ
Figure 7. Serial-Interface Timing Diagram
Serial Programming Interface
A serial interface programs the MAX19516 control registers through the CS, SDIN, and SCLK inputs. Serial data is shifted into SDIN on the rising edge of SCLK when CS is low. The MAX19516 ignores the data presented at SDIN and SCLK when CS is high. CS must transition high after each read/write operation. SDIN also serves as the serial-data output for reading control registers. The serial interface supports two-byte transfer in a communication cycle. The first byte is a control byte, containing the address and read/write instruction, written to the MAX19516. The second byte is a data byte and can be written to or read from the MAX19516. Figure 6 shows a serial-interface communication cycle. The first SDIN bit clocked in establishes the communi-
cation cycle as either a write or read transaction (0 for write operation and 1 for read operation). The following 7 bits specify the address of the register to be written or read. The final 8 SDIN bits are the register data. All address and data bits are clocked in or out MSB first. During a read operation, the MAX19516 serial port drives read data (D7) into SDIN after the falling edge of SCLK following the 8th rising edge of SCLK. Since the minimum hold time on SDIN input is zero, the master can stop driving SDIN any time after the 8th rising edge of SCLK. Subsequent data bits are driven into SDIN on the falling edge of SCLK. Output data in a read operation is latched on the rising edge of SCLK. Figure 7 shows the detailed serial-interface timing diagram.
16
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Dual-Channel, 10-Bit, 100Msps ADC
Register address 0Ah is a special-function register. Writing data 5Ah to register 0Ah initiates a register reset. When this operation is executed, all control registers are reset to default values. A read operation of register 0Ah returns a status byte with information described in Table 2.
MAX19516
Table 2. Register 0Ah Status Byte
BIT NO. 7 6 5 4 3 2 1 0 VALUE 0 0 0 or 1 0 or 1 0 1 0 or 1 0 or 1 Reserved Reserved 1 = ROM read in progress 1 = ROM read completed and register data is valid (checksum is OK) Reserved Reserved Reserved 1 = Duty-cycle equalizer DLL is locked DESCRIPTION
User-Programmable Registers
Table 3. User-Programmable Registers
ADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 0Ah POR DEFAULT 00000011 00000000 00000000 10110110 00000000 00000000 00000000 Reserved 00000000 -- Power management Output format Digital output power management Data/DCLK timing CHA data output termination control CHB data output termination control Clock divide/data format/test pattern Reserved--do not use Common mode Software reset FUNCTION
Power Management (00h)
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 HPS_SHDN1 STBY_SHDN1 CHB_ON_SHDN1 CHA_ON_SHDN1 HPS_SHDN0 STBY_SHDN0 CHB_ON_SHDN0 CHA_ON_SHDN0
The SHDN input (pin 7) toggles between any two power-management states. The Power Management register defines each power-management state. In the
default state, SHDN = 1 shuts down the MAX19516 and SHDN = 0 returns to full power.
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17
Dual-Channel, 10-Bit, 100Msps ADC MAX19516
In addition to power management, the HPS_SHDN1 and HPS_SHDN0 activate an A+B adder mode. In this mode, the results from both channels are averaged. The MUX_CH bit selects which bus the (A+B)/2 data is presented.
Control Bits:
HPS_SHDN0 HPS_SHDN1 X 0 0 0 0 0 0 1 1 1 STBY_SHDN0 STBY_SHDN1 0 0 0 X 1 1 1 1 X X CHA_ON_SHDN0 CHA_ON_SHDN1 0 0 1 1 0 0 1 0 X 1 CHB_ON_SHDN0 CHB_ON_SHDN1 0 1 0 1 0 1 0 0 1 X SHDN INPUT = 0* SHDN INPUT = 1** Complete power-down Channel B active, channel A full power-down Channel A active, channel B full power-down Channels A and B active Channels A and B in standby mode Channel B active, channel A standby Channel A active, channel B standby Channels A and B in standby mode Channels A and B active, output is averaged Channels A and B active, output is averaged
*HPS_SHDN0, STBY_SHDN0, CHA_ON_SHDN0, and CHB_ON_SHDN0 are active when SHDN = 0. **HPS_SHDN1, STBY_SHDN1, CHA_ON_SHDN1, and CHB_ON_SHDN1 are active when SHDN = 1.
X = Don't care. Note: When HPS_SHDN_ = 1 (A+B adder mode), CHA_ON and CHB_ON must BOTH equal 0 for power-down or standby.
Output Format (01h)
BIT 7 0 BIT 6 0 BIT 5 0 BIT 4 BIT_ORDER_B BIT 3 BIT_ORDER_A BIT 2 MUX_CH BIT 1 MUX BIT 0 0
Bit 7, 6, 5 Bit 4
Set to 0 for proper operation BIT_ORDER_B: Reverse CHB output bit order 0 = Defined data bus pin order (default) 1 = Reverse data bus pin order BIT_ORDER_A: Reverse CHA output bit order 0 = Defined data bus pin order (default) 1 = Reverse data bus pin order
Bit 3
Bit 2
MUX_CH: Multiplexed data bus selection 0 = Multiplexed data output on CHA (CHA data presented first, followed by CHB data) (default) 1 = Multiplexed data output on CHB (CHB data presented first, followed by CHA data) MUX: Digital output mode 0 = Dual data bus output mode (default) 1 = Single multiplexed data bus output mode MUX_CH selects the output bus
Bit 1
Bit 0
Set to 0 for proper operation
18
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Dual-Channel, 10-Bit, 100Msps ADC
Digital Output Power Management (02h)
BIT 7 X BIT 6 X BIT 5 X BIT 4 X BIT 3 PD_DOUT_1 BIT 2 PD_DOUT_0 BIT 1 DIS_DOR BIT 0 DIS_DCLK
MAX19516
Bit 7-4 Bit 3, 2
Don't care PD_DOUT_1, PD_DOUT_0: Power-down digital output state control 00 = Digital output three state (default) 01 = Digital output low 10 = Digital output three state 11 = Digital output high
Bit 1
DIS_DOR: DOR driver disable 0 = DOR active (default) 1 = DOR disabled (three state)
Bit 0
DIS_DCLK: DCLK driver disable 0 = DCLK active (default) 1 = DCLK disabled (three state)
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19
Dual-Channel, 10-Bit, 100Msps ADC MAX19516
Data/DCLK Timing (03h)
BIT 7 DA_BYPASS BIT 6 DLY_HALF_T BIT 5 DCLKTIME_2 BIT 4 DCLKTIME_1 BIT 3 DCLKTIME_0 BIT 2 DTIME_2 BIT 1 DTIME_1 BIT 0 DTIME_0
Bit 7
DA_BYPASS: Data aligner bypass 0 = Nominal 1 = Bypasses data aligner delay line to minimize output data latency with respect to the input clock. Rising clock to data transition is approximately 6ns with DTIME = 000b settings (default) DLY_HALF_T: Data and DCLK delayed by T/2 0 = Normal, no delay (default) 1 = Delays data and DCLK outputs by T/2 Disabled in MUX data bus mode
Bit 6
Bit 5, 4, 3
DCLKTIME_2, DCLKTIME_1, DCLKTIME_0: DCLK timing adjust (controls both channels) 000 = Nominal 001 = +T/16 010 = +2T/16 011 = +3T/16 100 = Reserved, do not use 101 = -1T/16 110 = -2T/16 (default) 111 = -3T/16
Bit 2, 1, 0
DTIME_2, DTIME_1, DTIME_0: Data timing adjust (controls both channels) 000 = Nominal 001 = +T/16 010 = +2T/16 011 = +3T/16 100 = Reserved, do not use 101 = -1T/16 110 = -2T/16 (default) 111 = -3T/16
20
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Dual-Channel, 10-Bit, 100Msps ADC
CHA Data Output Termination Control (04h)
BIT 7 X BIT 6 X BIT 5 CT_DCLK_2_A BIT 4 CT_DCLK_1_A BIT 3 CT_DCLK_0_A BIT 2 CT_DATA_2_A BIT 1 CT_DATA_1_A BIT 0 CT_DATA_0_A
MAX19516
Bit 7, 6 Bit 5, 4, 3
Don't care CT_DCLK_2_A, CT_DCLK_1_A, CT_DCLK_0_A: CHA DCLK termination control 000 = 50 (default) 001 = 75 010 = 100 011 = 150 1xx = 300
Bit 2, 1, 0
CT_DATA_2_A, CT_DATA_1_A, CT_DATA_0_A: CHA data output termination control 000 = 50 (default) 001 = 75 010 = 100 011 = 150 1xx = 300
CHB Data Output Termination Control (05h)
BIT 7 X BIT 6 X BIT 5 CT_DCLK_2_B BIT 4 CT_DCLK_1_B BIT 3 CT_DCLK_0_B BIT 2 CT_DATA_2_B BIT 1 CT_DATA_1_B BIT 0 CT_DATA_0_B
Bit 7, 6 Bit 5, 4, 3
Don't care CT_DCLK_2_B, CT_DCLK_1_B, CT_DCLK_0_B: CHB DCLK termination control 000 = 50 (default) 001 = 75 010 = 100 011 = 150 1xx = 300
Bit 2, 1, 0
CT_DATA_2_B, CT_DATA_1_B, CT_DATA_0_B: CHB data output termination control 000 = 50 (default) 001 = 75 010 = 100 011 = 150 1xx = 300
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21
Dual-Channel, 10-Bit, 100Msps ADC MAX19516
Clock Divide/Data Format/Test Pattern (06h)
BIT 7 TEST_PATTERN BIT 6 TEST_DATA BIT 5 FORMAT_1 BIT 4 FORMAT_0 BIT 3 TERM_100 BIT 2 SYNC_MODE BIT 1 DIV1 BIT 0 DIV0
Bit 7
TEST_PATTERN: Test pattern selection 0 = Ramps from 0 to 1023 (offset binary) and repeats (subsequent formatting applied) (default) 1 = Data alternates between D[9:0] = 0101010101, DOR = 1, and D[9:0] = 1010101010, DOR = 0 on both channels TEST_DATA: Data test mode 0 = Normal data output (default) 1 = Outputs test data pattern FORMAT_1, FORMAT_0: Data numerical format 00 = Two's complement (default) 01 = Offset binary 10 = Gray code 11 = Two's complement
Bit 6
Bit 5, 4
Bit 3
TERM_100: Select 100 clock input termination 0 = No termination (default) 1 = 100 termination across differential clock inputs SYNC_MODE: Divider synchronization mode select 0 = Slip mode (Figure 11) (default) 1 = Edge mode (Figure 12) DIV1, DIV0: Input clock-divider select 00 = No divider (default) 01 = Divide-by-2 10 = Divide-by-4 11 = No divider
Bit 2
Bit 1, 0
Reserved (07h)--Do not write to this register
22
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Dual-Channel, 10-Bit, 100Msps ADC
Common Mode (08h)
BIT 7 CMI_SELF_B BIT 6 CMI_ADJ_2_B BIT 5 CMI_ADJ_1_B BIT 4 CMI_ADJ_0_B BIT 3 CMI_SELF_A BIT 2 CMI_ADJ_2_A BIT 1 CMI_ADJ_1_A BIT 0 CMI_ADJ_0_A
MAX19516
Bit 7
CMI_SELF_B: CHB connect input common-mode to analog inputs 0 = Internal common-mode voltage is NOT applied to inputs (default) 1 = Internal common-mode voltage applied to analog inputs through 2k resistors CMI_ADJ_2_B, CMI_ADJ_1_B, CMI_ADJ_0_B: CHB input common-mode voltage adjustment 000 = 0.900V (default) 001 = 1.050V 010 = 1.200V 011 = 1.350V 100 = 0.900V 101 = 0.750V 110 = 0.600V 111 = 0.450V
Bit 6, 5, 4
Bit 3
CMI_SELF_A: CHA connect input common-mode to analog inputs 0 = Internal common-mode voltage is NOT applied to inputs (default) 1 = Internal common-mode voltage applied to analog inputs through 2k resistors CMI_ADJ_2_A, CMI_ADJ_1_A, CMI_ADJ_0_A: CHA input common-mode adjustment 000 = 0.900V (default) 001 = 1.050V 010 = 1.200V 011 = 1.350V 100 = 0.900V 101 = 0.750V 110 = 0.600V 111 = 0.450V
Bit 2, 1, 0
Software Reset (0Ah)
Bit 7-0 SWRESET: Write 5Ah to initiate software reset
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23
Dual-Channel, 10-Bit, 100Msps ADC MAX19516
100 TERMINATION (PROGRAMMABLE) CLK+ AVDD 5k 50 10k 2:1 MUX
Clock Inputs
The input clock interface provides for flexibility in the requirements of the clock driver. The MAX19516 accepts a fully differential clock or single-ended logiclevel clock. For differential clock operation, connect a differential clock to the CLK+ and CLK- inputs. In this mode, the input common mode is established internally to allow for AC-coupling. The differential clock signal can also be DC-coupled if the common mode is constrained to the specified 1V to 1.4V clock input common-mode range. For single-ended operation, connect CLK- to GND and drive the CLK+ input with a logiclevel signal. When the CLK- input is grounded (or pulled below the threshold of the clock mode detection comparator) the differential-to-single-ended conversion stage is disabled and the logic-level inverter path is activated.
20k 50 5k GND CLKSELECT THRESHOLD
SELF-BIAS TURNED OFF FOR SINGLE-ENDED CLOCK OR POWER-DOWN.
Clock Divider
The MAX19516 offers a clock-divider option. Enable clock division either by setting DIV0 and DIV1 through the serial interface; see the Clock Divide/Data
Figure 8. Simplified Clock Input Schematic
DUAL-BUS OUTPUT MODE SAMPLING INSTANT SAMPLING INSTANT SAMPLING INSTANT SAMPLING INSTANT SAMPLING INSTANT
tAD IN_
SAMPLING INSTANT
tCLK SAMPLE ON RISING EDGE n SAMPLE CLOCK n+1 tCH n+2 n+3 tCL n+4 n+5
tDD DATA, DOR
n-10 tDC
n-9
n-8 tHOLD
n-7
n-6
n-5
n-4
tSETUP
DCLK SAMPLE CLOCK IS THE DERIVED CLOCK FROM (CLK+ - CLK-)/CLOCK DIVIDER, IN_ = IN_+ - IN_-.
Figure 9. Dual-Bus Output Mode Timing
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Dual-Channel, 10-Bit, 100Msps ADC MAX19516
MUX OUTPUT MODE
SAMPLING INSTANT SAMPLING INSTANT SAMPLING INSTANT
SAMPLING INSTANT
tAD
SAMPLING INSTANT
IN_
SAMPLING INSTANT
tCLK SAMPLE ON RISING EDGE n n+1 tCH n+2 n+3 tCL n+4 n+5
SAMPLE CLOCK
tDD CHB CHA n-9 tDC CHB n-9
tCHA CHA n-8 tDCH tDCL CHB n-8 CHA n-7
tCHB CHB n-7 tSETUP CHA n-6 tHOLD tSETUP CHB n-6 CHA n-5 CHB n-5 tHOLD CHA n-4 CHB n-4
DATA, DOR
n-10
DCLK
SAMPLE CLOCK IS THE DERIVED CLOCK FROM (CLK+ - CLK-)/CLOCK DIVIDER, IN_ = IN_+ - IN_-. MUX_CH (BIT 2, OUTPUT FORMAT 01h) DETERMINES THE OUTPUT BUS AND WHICH CHANNEL DATA IS PRESENTED.
Figure 10. Multiplexed Output Mode Timing
Format/Test Pattern register (06h) for clock-divider options, or in parallel programming configuration (SPEN = 1) by using the DIV input.
System Timing Requirements
Figures 9 and 10 depict the relationship between the clock input and output, analog input, sampling event, and data output. The MAX19516 samples on the rising edge of the sampling clock. Output data is valid on the next rising edge of DCLK after a nine-clock internal latency. For applications where the clock is divided, the sample clock is the divided internal clock derived from: [(CLK+ - CLK-)/DIVIDER]
two mechanisms to synchronize the internal clock: slip synchronization and edge synchronization. Select the synchronization mode using SYNC_MODE (bit 2) in the Clock Divide/Data Format/Test Pattern register (06h) and drive the SYNCIN input high to synchronize. Slip Synchronization Mode, SYNC_MODE = 0 (default): On the third rising edge of the input clock (CLK) after the rising edge of SYNC (provided set-up and hold times are met), the divided output is forced to skip a state transition (Figure 11). Edge Synchronization Mode, SYNC_MODE = 1: On the third rising edge of the input clock (CLK) after the rising edge of SYNC (provided set-up and hold times are met), the divided output is forced to state 0. A divided clock rising edge occurs on the fourth (/2 mode) or fifth (/4 mode) rising edge of CLK, after a valid rising edge of SYNC (Figure 12).
Synchronization When using the clock divider, the phase of the internal clock can be different than that of the FPGA, microcontroller, or other MAX19516s in the system. There are
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25
Dual-Channel, 10-Bit, 100Msps ADC MAX19516
tHO tSUV SYNCIN tSUV = SET-UP TIME FOR VALID CLOCK EDGE. tHO = HOLD-OFF TIME FOR INVALID CLOCK EDGE.
DIVIDE-BY-2 SLIP SYNCRONIZATION
1 2x INPUT CLK
2
3
4
SLIP (0) 1x DIVIDED CLK (STATE) (1) (0) (1) (1) (0) (1) (0) (1) (0) (1) (0) (1) (1) (0) (0) (1) (0) (1) (0) (1) (0) (1) (0)
tHO tSUV SYNCIN DIVIDE-BY-4 SLIP SYNCHRONIZATION
1 4x INPUT CLK
2
3
4
5
SLIP (0) (1) (2) (3) (3) (0) (1) (2) (3) (0) (1) (2) (3)
(1) 1x DIVIDED CLK (STATE) (2)
(2)
(3)
(0)
(0)
(1)
(2)
(3)
(0)
(1)
(2)
(3)
(0)
(3)
(0)
(1)
(1)
(2)
(3)
(0)
(1)
(2)
(3)
(0)
(1)
(3)
(0)
(1)
(2)
(2)
(3)
(0)
(1)
(2)
(3)
(0)
(1)
(2)
Figure 11. Slip Synchronization Mode
26
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Dual-Channel, 10-Bit, 100Msps ADC MAX19516
tHO tSUV SYNCIN 1 2x INPUT CLK FORCE TO 0 (0) 1x DIVIDED CLK (STATE) (1) (0) (1) (0) (1) (0) (1) (0) (1) (0) (1) (0) (1) (1) (0) (0) (1) (0) (1) (0) (1) (0) (1) (0) (1) 2 tSUV = SET-UP TIME FOR VALID CLOCK EDGE. tHO = HOLD-OFF TIME FOR INVALID CLOCK EDGE.
DIVIDE-BY-2 EDGE SYNCRONIZATION
3
4
tHO tSUV SYNCIN 1 4x INPUT CLK FORCE TO 0 (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) (2) (3) (0) (1) 2 3 4 DIVIDE-BY-4 EDGE SYNCHRONIZATION
5
(1) 1x DIVIDED CLK (STATE) (2)
(2)
(3)
(0)
(0)
(1)
(2)
(3)
(0)
(1)
(2)
(3)
(0)
(1)
(3)
(0)
(1)
(0)
(1)
(2)
(3)
(0)
(1)
(2)
(3)
(0)
(1)
(3)
(0)
(1)
(2)
(0)
(1)
(2)
(3)
(0)
(1)
(2)
(3)
(0)
(1)
Figure 12. Edge Synchronization Mode
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27
Dual-Channel, 10-Bit, 100Msps ADC MAX19516
Table 4. Data Timing Controls
DATA TIMING CONTROL DA_BYPASS DLY_HALF_T DTIME<2:0> DCLKTIME<2:0> DESCRIPTION Data aligner bypass. When this control is active (high), data and DCLK delay is reduced by approximately 2.6ns (relative to DA_BYPASS = 0). When this control is active, data output is delayed by half clock period (T/2). This control does not delay data output if MUX mode is active. Allows adjustment of data output delay in T/16 increments, where T is the sample clock period. Provides adjustment of DCLK delay in T/16 increments, where T is the sample clock period. When DTIME and DCLKTIME are adjusted to the same setting, the rising edge of DCLK occurs T/8 prior to data transitions.
Table 5. Data Timing Control Default Settings
DATA TIMING CONTROL DA_BYPASS DLY_HALF_T DTIME<2:0> DCLKTIME<2:0> DEFAULT 1 0 110 110 DESCRIPTION Data aligner disabled No delay -2T/16 (1.25ns at 100Msps) -2T/16 (1.25ns at 100Msps)
Digital Outputs
The MAX19516 features a dual CMOS, multiplexable, reversible data bus. In parallel programming mode, configure the data outputs (D0_-D9_) for offset binary, two's complement, or gray code using the FORMAT input. Select multiplexed or dual-bus operation using the OUTSEL input. See the Output Format register (01h) for details on output formatting using the SPI interface. The SPI interface offers additional flexibility where D0_-D9_ are reversed, so the LSB appears at D9_ and the MSB at D0_. OVDD sets the output voltage; set OVDD between 1.8V and 3.3V. The digital outputs feature programmable output impedance from 50 to 300. Set the output impedance for each bus using the CH_ Data Output Termination Control registers (04h and 05h).
The solid lines are the nominal data timing characteristics for the 14 available states of DTIME and DLY_HALF_T. The heavy line represents the nominal data timing characteristics for the default settings. Note that the default timing adjustment setting for the MAX19516 100Msps ADC results in an additional period of data latency. Tables 6 and 7 show the recommended timing control settings versus sampling rate. The nominal data timing characteristics versus sampling rate for these recommended timing adjustment settings are shown in Figures 15 and 16. When DA_BYPASS = 1, the DCLKTIME delay setting must be equal to or less than the DTIME delay setting, as shown in Table 8.
Power Management
The SHDN input (pin 7) toggles between any two powermanagement states. The Power Management register (00h) defines each power-management state. In default state, SHDN = 1 shuts down the MAX19516 and SHDN = 0 returns to full power. Use of the SHDN input is not required for power management. For either state of SHDN, complete power-management flexibility is provided, including individual ADC channel power-management control, through the Power Management register (00h). The available reduced-power modes are shutdown and standby. In standby mode, the reference and duty-cycle equalizer circuits remain active for rapid wake-up time. In standby mode, the externally applied clock signal must remain active for the duty-cycle equalizer to remain locked. Typical wake-up time from standby mode is 15s. In shutdown mode, all circuits are turned off except for the reference circuit required for the integrated self-sensing voltage regulator. If the regulator is active, there is additional supply current associated with the regulator circuit when the device is in shutdown. Typical wake-up time from shutdown mode is 5ms, which is dominated by the RC time constant on REFIO.
Programmable Data Timing The MAX19516 provides programmable data timing control to allow for optimization of timing characteristics to meet the system timing requirements. The timing adjustment feature also allows for ADC performance improvements by shifting the data output transition away from the sampling instant. The data timing control signals are summarized in Table 4. The default settings for timing adjustment controls are given in Table 5. Many applications will not require adjustment from the default settings.
The effects of the data timing adjustment settings are illustrated in Figures 13 and 14. The x axis is sampling rate and the y axis is data delay in units of clock period.
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Dual-Channel, 10-Bit, 100Msps ADC MAX19516
FACTORY DEFAULT NOMINAL DATA TIMING vs. SAMPLING RATE
2.0 DATA DELAY (T FRACTIONAL PERIOD) DATA DELAY (T FRACTIONAL PERIOD) OVDD = 1.8V DA_BYPASS = 1 1.5
+11/16 +9/16 +7/16 +5/16 +3/16 +1/16 -1/16 -3/16 +10/16 +8/16 +6/16 +2/16 0 -2/16
RECOMMENDED DATA TIMING vs. SAMPLING RATE
2.0 OVDD = 1.8V DA_BYPASS = 1 1.5
+11/16 +9/16 +7/16 +5/16 +3/16 +1/16 -1/16 -3/16 +10/16 +8/16 +6/16 +2/16 0 -2/16
1.0
1.0
0.5
0.5
0 50 60 70 80 90 100 SAMPLING RATE (Msps)
0 50 60 70 80 90 100 SAMPLING RATE (Msps)
Figure 13. Default Data Timing (VOVDD = 1.8V)
FACTORY DEFAULT NOMINAL DATA TIMING vs. SAMPLING RATE
2.0 DATA DELAY (T FRACTIONAL PERIOD)
Figure 15. Recommended Data Timing (VOVDD = 1.8V)
RECOMMENDED DATA TIMING vs. SAMPLING RATE
2.0 DATA DELAY (T FRACTIONAL PERIOD) OVDD = 3.3V DA_BYPASS = 1 1.5
+11/16 +9/16 +7/16 +5/16 +3/16 +1/16 -1/16 -3/16
OVDD = 3.3V DA_BYPASS = 1 1.5
+11/16 +9/16 +7/16 +5/16 +3/16 +1/16 -1/16 -3/16
1.0
+10/16 +8/16 +6/16 +2/16 0 -2/16
1.0
+10/16 +8/16 +6/16 +2/16 0 -2/16
0.5
0.5
0 50 60 70 80 90 100 SAMPLING RATE (Msps)
0 50 60 70 80 90 100 SAMPLING RATE (Msps)
Figure 14. Default Data Timing (VOVDD = 3.3V)
Figure 16. Recommended Data Timing (VOVDD = 3.3V)
Table 6. Recommended Timing Adjustments (VOVDD = 1.8V)
SAMPLING RATE (Msps) FROM 50 55 65 75 86 96 TO 55 65 75 86 96 100 DA_BYPASS 1 1 1 1 1 1 0 0 0 1 1 1 VOVDD = 1.8V DLY_HALF_T DTIME<2:0> 101 110 111 011 010 001 DCLKTIME<2:0> 101 110 111 011 010 001
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29
Dual-Channel, 10-Bit, 100Msps ADC MAX19516
Table 7. Recommended Timing Adjustments (VOVDD = 3.3V)
SAMPLING RATE (Msps) FROM 50 63 77 91 TO 63 77 91 100 DA_BYPASS 1 1 1 1 0 0 0 0 VOVDD = 3.3V DLY_HALF_T DTIME<2:0> 000 101 110 111 DCLKTIME<2:0> 000 101 110 111
Table 8. Allowed Settings of DCLKTIME and DTIME for DA_BYPASS = 1
DTIME<2:0> 111 (-3T/16) 110 (-2T/16) 101 (-1T/16) 000 (nominal) 001 (+1T/16) 010 (+2T/16) 011 (+3T/16) 111 (-3T/16) 110 (-2T/16); 111 (-3T/16) 101 (-1T/16); 110 (-2T/16); 111 (-3T/16) 000 (nominal); 101 (-1T/16); 110 (-2T/16); 111 (-3T/16) 001 (+1T/16); 000 (nominal); 101 (-1T/16); 110 (-2T/16); 111 (-3T/16) 010 (+2T/16); 001 (+1T/16); 000 (nominal); 101 (-1T/16); 110 (-2T/16); 111 (-3T/16) 011 (+3T/16); 010 (+2T/16); 001 (+1T/16); 000 (nominal); 101 (-1T/16); 110 (-2T/16); 111 (-3T/16) ALLOWED DCLKTIME<2:0> SETTINGS
Table 9. Reset Methods
RESET MODE Power-On Reset Software Reset DESCRIPTION Upon power-up (AVDD supply voltage and clock signal applied), the POR (power-on-reset) circuit initiates a register reset. Write data 5Ah to address 0Ah to initiate register reset.
Hardware Reset A register reset is initiated by the falling edge on the SHDN pin when SPEN is high.
Integrated Voltage Regulator
The MAX19516 includes an integrated self-sensing linear voltage regulator on the analog supply (AVDD). See Figure 17. When the applied voltage on AVDD is below 2V, the voltage regulator is bypassed, and the core analog circuitry operates from the externally applied voltage. If the applied voltage on AVDD is higher than 2V, the regulator bypass switches off, and voltage regulator mode is enabled. When in voltage regulation mode, the internal-core analog circuitry operates from a stable 1.8V supply voltage provided by the regulator. The regulator provides an output voltage of 1.8V over a 2.3V to 3.5V AVDD input-voltage range. Since the power-supply current is constant over this voltage range, analog power dissipation is proportional to the applied voltage.
Power-On and Reset
The user-programmable register default settings and other factory-programmed settings are stored in nonvolatile memory. Upon device power-up, these values are loaded into the control registers. This operation occurs after application of supply voltage to AVDD and application of an input clock signal. The register values are retained as long as AVDD is applied. While AVDD is applied, the registers can be reset, which will overwrite all user-programmed registers with the default values. This reset operation can be initiated by software command through the serial-port interface or by hardware control using the SPEN and SHDN inputs. The reset time is proportional to the ADC clock period and requires 85s at 100Msps. Table 9 summarizes the reset methods.
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Dual-Channel, 10-Bit, 100Msps ADC MAX19516
AVDD (PINS 1, 12, 13, 48)
REGULATOR IN 2.3V TO 3.5V ENABLE REFERENCE OUT 1.8V INTERNAL ANALOG CIRCUITS
GND
Figure 17. Integrated Voltage Regulator
Applications Information
IN_+
Analog Inputs
Transformer-Coupled Differential Analog Input The MAX19516 provides better SFDR and THD with fully differential input signals than a single-ended input drive. In differential input mode, even-order harmonics are lower as both inputs are balanced, and each of the ADC inputs only require half the signal swing compared to single-ended input mode. An RF transformer (Figure 18) provides an excellent solution for converting a single-ended signal to a fully differential signal. Connecting the center tap of the transformer to CM_ provides a common-mode voltage. The transformer shown has an impedance ratio of 1:1.4. Alternatively, a different step-up transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver can also improve the overall distortion. The configuration of Figure 18 is good for frequencies up to Nyquist (fCLK/2).
0.1F VIN N.C.
1 T1 5
6 2
36.5 0.5%
MAX19516
CM_ 0.1F
N.C.
3 4 MINI-CIRCUITS 36.5 0.5% ADT1-1WT
IN_-
Figure 18. Transformer-Coupled Input Drive for Input Frequencies Up to Nyquist
IN_+ 0.1F VIN N.C. 1 5 T1 6 2 75 0.5% N.C. 75 0.5% N.C. 1 5 T2 6 2
110 0.5%
MAX19516
N.C. 0.1F CM_
3 4 MINI-CIRCUITS ADT1-1WT
3 4 MINI-CIRCUITS ADT1-1WT
110 0.5% IN_-
Figure 19. Transformer-Coupled Input Drive for Input Frequencies Beyond Nyquist
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Dual-Channel, 10-Bit, 100Msps ADC MAX19516
VIN
MAX4108
0.1F IN_+ 100
CLKIN 0.1F 49.9
0.01F CLK+
MAX19516
CM_ 100 0.1F
49.9 0.01F
MAX19516
IN_0.1F
CLK-
Figure 20. Single-Ended, AC-Coupled Input Drive
Figure 21. Single-Ended-to-Differential Clock Input
The circuit of Figure 19 also converts a single-ended input signal to a fully differential signal. Figure 19 utilizes an additional transformer to improve the commonmode rejection allowing high-frequency signals beyond the Nyquist frequency. A set of 75 and 110 termination resistors provide an equivalent 50 termination to the signal source. The second set of termination resistors connect to CM_ providing the correct input common-mode voltage.
produce the highest level of signal integrity. Route highspeed digital signal traces away from the sensitive analog traces of either channel. Make sure to isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk. Keep all signal lines short and free of 90 turns.
Definitions
Integral Nonlinearity (INL)
INL is the deviation of the measured transfer function from a best-fit straight line. Worst-case deviation is defined as INL.
Single-Ended AC-Coupled Input Signal Figure 20 shows a single-ended, AC-coupled input application. The MAX4108 provides high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity. Bias voltage is applied to the inputs through internal 2k resistors. See Common Mode register 08h for further details. DC-Coupled Input The MAX19516's wide common-mode voltage range (0.4V to 1.4V) allows DC-coupled signals. Ensure that the common-mode voltage remains between 0.4V and 1.4V.
Differential Nonlinearity (DNL)
DNL is the difference between the measured transfer function step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. DNL deviations are measured at each step of the transfer function and the worst-case deviation is defined as DNL.
Offset Error
Offset error is a parameter that indicates how well the actual transfer function matches the ideal transfer function at midscale. Ideally, the midscale transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point.
Clock Input
Figure 21 shows a single-ended-to-differential clock input converting circuit.
Grounding, Bypassing, and Board-Layout Considerations
The MAX19516 requires high-speed board-layout design techniques. Locate all bypass capacitors as close as possible to the device, preferably on the same side as the ADC, using surface-mount devices for minimum inductance. Bypass AVDD, OVDD, REFIO, CMA, and CMB with 0.1F ceramic capacitors to GND. Multilayer boards with ground and power planes
Gain Error
Gain error is a figure of merit that indicates how well the slope of the measured transfer function matches the slope of the ideal transfer function based on the specified full-scale input-voltage range. The gain error is defined as the relative error of the measured transfer function and is expressed as a percentage.
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Dual-Channel, 10-Bit, 100Msps ADC
Small-Signal Noise Floor (SSNF)
SSNF is the integrated noise and distortion power in the Nyquist band for small-signal inputs. The DC offset is excluded from this noise calculation. For this converter, a small signal is defined as a single tone with an amplitude less than -35dBFS. This parameter captures the thermal and quantization noise characteristics of the converter and can be used to help calculate the overall noise figure of a receive channel. Refer to www.maxim-ic.com for application notes on Thermal + Quantization Noise Floor.
Single-Tone Spurious-Free Dynamic Range (SFDR1 and SFDR2)
SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS amplitude of the next largest spurious component, excluding DC offset. SFDR1 reflects the spurious performance based on worst 2nd-order or 3rd-order harmonic distortion. SFDR2 is defined by the worst spurious component excluding 2nd- and 3rdorder harmonics and DC offset.
MAX19516
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N bits): SNR[max] = 6.02 x N + 1.76 In reality, there are other noise sources besides quantization noise (e.g., thermal noise, reference noise, clock jitter, etc.). SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first six harmonics (HD2-HD7), and the DC offset. SIGNALRMS SNR = 20 x log NOISERMS
Total Harmonic Distortion (THD)
THD is the ratio of the RMS of the first six harmonics of the input signal to the fundamental itself. This is expressed as:
V22 + V32 + V4 2 + V52 + V62 + V72 THD = 20 x log V1
where V1 is the fundamental amplitude and V2-V7 are the amplitudes of the 2nd-order through 7th-order harmonics (HD2-HD7).
Third-Order Intermodulation (IM3)
IM3 is the total power of the third-order intermodulation products to the Nyquist frequency relative to the total input power of the two input tones fIN1 and fIN2. The individual input tone levels are at -7dBFS. The thirdorder intermodulation products are: 2 x fIN1 - fIN2, 2 x fIN2 - fIN1, 2 x fIN1 + fIN2, 2 x fIN2 + fIN1.
Aperture Delay
The input signal is sampled on the rising edge of the sampling clock. There is a small delay between the rising edge of the sampling clock and the actual sampling instant, which is defined as aperture delay (tAD).
Signal-to-Noise and Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus the RMS distortion. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first six harmonics (HD2-HD7), and the DC offset. RMS distortion includes the first six harmonics (HD2-HD7).
SIGNALRMS SINAD = 20 x log 2 2 NOISERMS + DISTORTIONRMS
Aperture Jitter
Aperture jitter (tAJ) is defined as the sample-to-sample time variation in the aperture delay.
Overdrive Recovery Time
Overdrive recovery time is the time required for the ADC to recover from an input transient that exceeds the full-scale limits. The specified overdrive recovery time is measured with an input transient that exceeds the fullscale limits by 10%.
Process Information
PROCESS: CMOS
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33
Dual-Channel, 10-Bit, 100Msps ADC MAX19516
Pin Configuration
OVDD OVDD
D3A
D2A
D1A
D0A
D9B
D8B
D7B
D6B
D5B
36 35 34 33 32 31 30 29 28 27 26 25 D4A D5A D6A D7A D8A D9A DORA DCLKA SDIN/FORMAT SCLK/DIV CS/OUTSEL AVDD 37 38 39 40 41 42 43 44 45 46 47 48 1 AVDD 2 CMA 3 INA+ 4 INA5 SPEN 6 REFIO 7 SHDN 8 I.C. 9 INB+ 10 11 12 INBCMB AVDD 24 23 22 21 20 19 D3B D2B D1B D0B DCLKB DORB GND GND CLKCLK+ SYNC AVDD
MAX19516
D4B
TOP VIEW
18 17 16 15
+
*EP
14 13
*EXPOSED PAD
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 48 TQFN-EP PACKAGE CODE T4877-4 DOCUMENT NO. 21-0144
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Dual-Channel, 10-Bit, 100Msps ADC
Revision History
REVISION NUMBER 0 1 REVISION DATE 7/08 10/08 Initial release Corrected error in vertical scale for TOC 32 DESCRIPTION PAGES CHANGED -- 11
MAX19516
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 35
(c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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